As customer demand grows for smaller and more portable devices, size reduction becomes an increasingly important objective for electronic device manufacturers. Manufacturers continue to search for ways to pack more functionality and higher performance into small electronic devices. However, increasing functionality and performance frequently requires adding components into an electronic device, which can increase the device size. One approach is to combine numerous separate components or devices into a single component or package. With regard to semiconductor devices, this has taken several forms. On one hand, semiconductor device manufacturers may design more than one kind of semiconductor device onto a single ‘chip’, but this can grow the chip area, consuming more space on a substrate in the electronic device. On the other hand, semiconductor device manufacturers may stack numerous individual semiconductor chips into a single stack. Of these two approaches, the latter has the benefit of reducing the amount of surface area consumed on a substrate to which such a stacked semiconductor device package is attached.
To form the stack of individual chips, manufactures typically attach one chip (bottom chip) to a substrate, then attach each successively higher chip in the stack to the either the bottom chip, or to the chip last added to the stack. Alternately, chips may be attached to form a stack prior to attaching it to a substrate, with gaps existing between each of the chips in the stack.
The gaps between chips are filled with an underfill material to further bond the chips together to help prevent defects that may be caused by thermal stresses resulting from different coefficients of thermal expansion (CTE) between the chips in the stack. Typically, an underfill material is first deposited at the junction of the bottom chip and the substrate, and the underfill material is drawn beneath the chip by capillary action. A fillet of underfill material forms around the periphery of the chip, adhering to the substrate and to at least a portion of the outer edge of the chip. A second deposition of underfill material is disposed atop this fillet, and the underfill material is built up so that it contacts at least a portion of an edge of the bottom chip and a portion of an edge of the next higher (second) chip in the stack, therefore causing the underfill material to be drawn into and through the gap between the bottom chip and the second chip. A fillet forms around the periphery of the second chip, and the process described above is repeated again once for each gap between chips in the stack. Finally, a fillet is formed in contact with at least a portion of the uppermost chip in the stack. The combination of all the fillets formed during this process creates a single large fillet extending a substantial distance away from the periphery of the stack of chips, and in simultaneous contact with the surface of the substrate and with each and every chip in the stack of chips. Underfill material may be cured after each deposition, or it may all be cured in a single operation after all gaps in the stack are filled.
Numerous problems are inherent in this process. It requires a substantial amount of time to complete the iterative underfill application process and form a finished stack. The large underfill fillet typically extends a substantial distance away from the stacked chips, forming an ‘overrun tongue’ that consumes a notably larger amount of substrate surface area than is covered by the stack itself. This tongue prevents other components from being placed close to a chip stack, which can create both design, and as a result, performance problems. With regard to design problems, it forces other components to be placed more densely within the size constraints of a device design, or alternatively, may force the device size to be increased to accommodate the spatial inefficiencies of the large fillets. With regard to performance, some semiconductor devices perform less efficiently if the transmission lines from the device to associated components (e.g., capacitors) are too long. A large fillet may force capacitors to be placed onto a substrate far enough away from a device that device performance is negatively affected.
Further, a large amount of underfill material may be needed to not only fill the gaps, but to also form an increasingly high base for each subsequent deposition of underfill material. Nearly all of the underfill not filling the gaps between chips or between the bottom chip and the substrate surface, may be considered wasted material. Additionally, the large amount of underfill material requires a substantial amount of time to cure. Within the stack itself, the chips may not each be the same size, or the edges of the chips may not align with the corresponding edges of every other chip in the stack. Such non-aligned edges may create difficulties in chip handling, and may also negatively effect the efficiency of the underfill process. Further, as the underfill material migrates within the gaps between chips and outward to form the peripheral fillets, no alignment or uniform periphery is formed with regard to any chip in the stack related to any other chip in the stack, nor with regard to the underfill material related to any chip in the stack. Rather, an irregular, sloping periphery (fillet) is formed in most cases.
Another notable defect inherent in the method described above is void formation. Capillary underfill, migrating into and through a gap between adjacent chips, is known to migrate at different rates depending on the number of obstructions that may exist in its path, such as may be formed by an array of interconnections between two chips. In such cases, with capillary action alone pulling the underfill material through the gap, underfill material may migrate entirely around an array of interconnections before the gap within the array is filled. In these situations, a void of trapped air can remain in the center of the array completely surrounded by underfill material, and therefore, the interconnections within the array may not be adequately stabilized against CTE damage, and device failure may result.
Taken together, the above described problems associated with existing stacked chip solutions account for a substantial amount of yield reduction in semiconductor manufacturing operations, as well as cost and design inefficiencies.